In the field of integrated circuit devices, particularly programmable devices, it is desirable to move a signal as fast as possible along its path to a destination. It is also desirable to minimize the area of an integrated circuit device needed to implement a function. Thus speed should be maximized and area should be minimized. In the case of multiplexers, memory cells are frequently used to control a multiplexer. It is widely known that two memory cells can select between up to four input signals and three memory cells can select between up to eight input signals.
FIGS. 1-3 show three prior art structures for controlling six-input multiplexers. In FIG. 1, the selection is done by providing a transistors tree, each memory cell selecting a branch of the tree. Memory cell M1 controls N-channel transistors T1, T3, and T5 from its inverting output and transistors T2, T4, and T6 from its noninverting output. A logical 0 in memory cell M1 causes transistors T1, T3, and T5 on and thus forwards input signals IN0, IN2, and IN4 to the next level. Memory cell M2 selects between transistors T7 and T8. If memory cell M2 holds a logical 0, the signal from one of IN0 and IN1 is forwarded to the next level and if memory cell M2 holds a logical 1, the signal from one of IN2 and IN3 is forwarded to the next level. Finally, memory cell M3 controls transistors T9 and T10, and selects between the signal forwarded from one of IN0 through IN3 and the signal forwarded from one of IN4 and IN5. In this embodiment, a signal on IN0 must pass through three transistors, T1, T7, and T9 to reach the OUT terminal. Thus the signal path is slower than desirable.
Alternatively, in FIG. 2, the selection is done by providing one decoder for each input line and turning on a different transistor to enable a different input signal in response to a different combination of signals from the memory cells. For example, AND-gate decoder D1 provides a high output signal when all three of memory cells M1-M3 hold logical 0, turning on transistor T21 and providing the signal on IN0 to OUT. Other memory cell combinations provide one of the other input signals IN0-IN5 as the output signal. Only one transistor is in the signal path, but the control signal must pass through a decoder, and silicon area must be used to provide the decoders. Thus the structure of FIG. 2 is faster but larger than the structure of FIG. 1.
FIG. 3 shows a six-input multiplexer that uses four memory cells and requires the input signal to pass through two transistors to reach the output terminal. Memory cells M1-M3 each select one signal from each of two sets of three input signals. Only one of memory cells M1 through M3 is permitted to hold a logical 1 at one time. When memory cell M1 holds logical 1, it turns on transistors T31 and T34. A logical 1 in memory cell M2 turns on transistors T32 and T35, A logical 1 in memory cell M3 turns on transistors T33 and T36. Memory cell M4 chooses which of the selected input signals is provided to the OUT terminal. This prior art multiplexer places two transistors into each signal path. It uses no decoders, but requires four memory cells.
Other multiplexers are also known. For example, six memory cells can select between six input signals placing only one transistor into the signal path. Three memory cells can control an 8:1 multiplexer with only one transistor in the signal path using decode logic, but this decode logic typically takes more area than an additional memory cell. Larger multiplexers can be formed by combining structures similar to those shown in FIGS. 1-3.
It has not been known in the past that a six input multiplexer can be provided without decoders to select between more than four input signals using only two transistors in a signal path.